1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device with redundant memories for relieving defective memories.
2. Description of the Related Art
It is well-known that conventional DRAMs, SRAMs, and EEPROMs are provided with a redundant memory for relieving defective cells. For instance, a 64-Mbit memory, which contains more than 67 million memory cells, is provided with a redundant memory composed of auxiliary memory cells. In order to enable the memory device to function as a 64-Mbit memory even if several memory cells fail, the auxiliary memory cells are replaced with the defective memory cells. The memory device also contains ROMs which, in general, are composed of polysilicon fuses, for storing the addresses of defective cells. Defective-cell addresses are stored by cutting off the fuses. The circuit of the memory device is designed such that the redundant memory is accessed in case where the address signal coincides with the defective-cell address when the stored defective-cell address is compared with the address signal.
FIG. 1 is a timing chart showing the timing for selecting a redundant column in a conventional memory cell array. Defective-column addresses are stored in the redundant-section select circuit in the form of fuses. This causes a time lag t.sub.AR from when the address signal has been outputted until it is sensed whether or not the redundant section is selected and then a redundant-section select signal and a redundant-column address signal are outputted. In FIG. 1, t.sub.RS is the time from when the redundant-section select signal or redundant-column address signal is outputted until the column is activated, t.sub.SH is the column activating time, and t.sub.SA is the time from when the column is inactivated until the next column address signal is outputted.
However, with the conventional circuit configuration of the memory device, because it is sensed whether the address is to be used for a defective cell after the address signal has been determined, there is a waiting time between the determination of the address and memory accessing. This makes the access time longer, thus retarding the input and output of the data. As described above, with the conventional semiconductor memory device, use of a circuit for relieving defective memory cells makes the access time longer, giving rise to the problem of being unable to input and output data at high speeds.